17 Tháng Tám 12/11/09 PM Page ii Commonly used Power and Converter Equations Instantaneous power: p(t) ϭ v(t)i(t) t2 Energy: W. 13 Tháng Năm Voltage Regulators With the TL Patrick Griffith Standard Linear and Logic ABSTRACT The TL power-supply controller is discussed in. Công ty cổ phần Entertech Việt nam. Bảng điện tử sản xuất LED · BẢNG ĐIỆN TỬ LED đ. Bảng thông tin sản xuất tactime cho nhà máy cơ khí đ.
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As the control signal increases, the time during which the sawtooth input is greater decreases; therefore, the output dien tu cong suat duration decreases. Ut of output pulses is accomplished by comparing the sawtooth waveform created by the internal oscillator on the timing capacitor C T to either of two control signals.
Both high-gain error amplifiers receive their bias from the V I supply rail. A general overview dien tu cong suat the Skat architecture presents the primary functional blocks contained in the device. This ensures positive control of the output within one-half cycle for operation within the recommended kHz range.
Otherwise, the maximum output pulse width is limited. A general overview of the TL architecture presents.
The output stage is enabled during the time when the sawtooth voltage is greater conng dien tu cong suat voltage control signals. Figure 11 shows the proper biasing dien tu cong suat for feedback gain control. A pulse-steering flip-flop alternately directs the modulated pulse to each of the two output transistors. The amplifier outputs are biased low by a current sink to provide maximum pulse width out conh both amplifiers are biased off. The oscillator charges the external timing capacitor, C Twith a constant current, the value of which is determined by the external timing resistor, R T.
Attention must be given to this node for biasing considerations in gain-control and external-control interface circuits. This is the minimum blanking pulse acceptable to ensure proper switching of the pulse-steering flip-flop.
Reference Voltage vs Input Voltage 3.
The purpose of this application report is to give the reader a thorough understanding of the TL, its features, its performance characteristics, and its limitations. The timing capacitor input incorporates a series diode that is omitted from the control signal input.
Applying a voltage to the dead-time control input can impose additional dead time. Figure 1 is a block diagram of the TL For input voltages less than 7 V, the regulator saturates within 1 V of the input and tracks it dien tu cong suat Figure 4.
Multiplex Structure of Error Amplifiers Figure This produces a linear-ramp voltage waveform. When the voltage across C T dien tu cong suat 3 V, the oscillator circuit discharges it, and the charging cycle is reinitiated.
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Figure 7 shows the relationship of internal dead time expressed in percent for various values of R T and Iden T. The dead-time control input is compared directly by the dead-time control comparator. Dien tu cong suat input of the comparator does not exhibit hysteresis, so protection against false triggering near the threshold must be provided.
TL Modulation Technique The control signals are derived from two sources: Short-circuit protection is provided to protect the internal reference and preregulator; 10 mA of load current is available for additional dien tu cong suat circuits. However, for proper control, the input must be terminated. The comparator has a response time of ns from either of the control-signal inputs to the output transistors, with only mV of overdrive.
The oscillator provides a positive sawtooth waveform dien tu cong suat the dead-time and PWM comparators for comparison to the various control signals. Cog permits a common-mode input congg range from —0.
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The error amplifiers also can be used to monitor the output dien tu cong suat and provide current limiting to the load. Figure 2 shows the relationship between the pulses and the signals. The PWM comparator compares the control signal created by the error amplifiers. With the control input biased to ground, the output is inhibited during the time that the sawtooth waveform is below mV. In addition to providing a stable reference, it acts as a preregulator and establishes a stable supply from which the output-control logic, pulse-steering flip-flop, oscillator, dead-time control comparator, and PWM comparator are dien tu cong suat.
With full-range control, the output can be controlled from external sources without disrupting the error amplifiers. The two functions are totally independent, therefore, each function is discussed separately.
This provides isolation gu the input supply for improved stability. With both outputs ORed together at the inverting input node of the PWM comparator, the amplifier demanding the minimum pulse out dominates. An in-depth study of the interrelationship between the functional blocks highlights versatility and limitations of the TL For this, the ramp voltage across timing capacitor C T is compared to the control signal present at the output of the error amplifiers. This allows each amplifier to pull up independently for a decreasing output pulse-width demand.
The TL dien tu cong suat many features that previously required several different control circuits. An open circuit is an undefined condition. The output of the comparator inhibits switching transistors Q1 and Q2 dien tu cong suat the voltage at the input is greater than the ramp voltage of the oscillator see Figure For push-pull applications, the output frequency is one-half the oscillator frequency.